EECS 31L: Introduction to Digital Logic Laboratory (Spring 2025)
Lab 2: Arithmetic Logic Unit (ALU)
(Revision: v1.0)
Due: April 27, 2025 (11:59 PM)
A central processing unit (CPU) is a core computational unit in a computer. Throughout this course, you will gradually build components of processors (CPUs), and at the end of the course, you will complete a basic single-cycle processor design. In this lab, you will build an important component in processors, arithmetic logic unit (ALU). ALU is a combinational logic circuit that performs arithmetic and bitwise logic operations on integer binary numbers.
1 Verilog Arithmetic Operations
As introduced in the lecture, Verilog supports the following arithmetic operations.
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Operation
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Description
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Operand Type
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Result Type
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A + B
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Addition
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A, B: numeric
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Numeric
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A - B
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Subtraction
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A, B: numeric
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Numeric
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A * B
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Multiplication
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A, B: numeric
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Numeric
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A / B
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Division
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A, B: numeric
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Numeric
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A % B
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Modulo
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A, B: numeric, not real
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Numeric, not real
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A ** B
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Exponent AB
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A, B: numeric
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Numeric
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{A, B}
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Concatenation
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A, B: numeric or array element
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Same as A
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N{A}
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Repetition
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A: numeric or array element
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Same as A
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A 32-bit adder (for unsigned integer addition) can be implemented with arithmetic operators as follows.
Code 1: 32-bit Full Adder
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` timescale 1 ns / 1 ps
// Module definition
module fa32 (A , B , Cin , Sum , C out );
// Define I / O signals
input [31:0] A ;
input [31:0] B ;
input Cin ;
output [31:0] Sum ;
output C out ;
// Describe FA behavior
assign { Cout , Sum } = A + B + Cin ; end module // 32 - bit full adder
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2 32-bit Arithmetic Logic Unit (ALU)
The arithmetic logic unit (ALU) is the core computing component in processors. ALU performs the arithmetic operations like addition and subtraction or bit-wise logical operations like AND and OR. In this section, you will design and test a 32-bit ALU in Verilog. The block diagram of 32-bit ALU is shown below.
The ALU takes two 32-bit operands (A in and B in) and produces one 32-bit output (ALU out). Accord- ing to the 4-bit control code, which comes from the 4-bit ALU control signal ALU ctrl, the ALU decides which arithmetic or logical operation (ALU operation) should be executed.
The values of the ALU control signals and the corresponding ALU operations are shown below.
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ALU Control Signals (4-bit)
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ALU Operation
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4’b0000
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AND
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4’b0001
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OR
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4’b0010
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Add
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4’b0110
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Subtract
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4’b0111
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Set Less Than (slt)
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4’b1100
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NOR
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4’b1111
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Equal comparison
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Note: The default function for the ALU is add.
• The Set Less Than operation (slt) compares the two operands (A in and B in). If A in is less than B in then ALU out would be 32’b1 (represented as a 32-bit binary number 32’b0000 0000 0000 0001), otherwise 32’b0.
• The Equal Comparison operation compares the two operands (A in and B in). If A in is equal to B in then ALU out would be 32’b1 (represented as a 32-bit binary number 32’b0000 0000 0000 0001), otherwise 32’b0.
• The zero output (which is 1 bit) is 1 when all 32 bits of the ALU out result are 0.
• The overflow output (which is 1 bit) is 1 when there is an overflow in Add or Subtract operations. For other operations overflow is always 0.
• In the Add operations, the carry out output (which is 1 bit) is set to 1 when you have carry out on the most significant bit (MSB). For other operations, carry out is always 0.
• The AND, OR, and NOR are bit-wise logical operations.
• The Set Less Than, Add, and Subtract are signed operations. Signed operation can be implemented by casting unsigned value (operand) using $signed(), For example:
ALU out = $signed(A in) & $signed(B in).
Use the following code template for your module definition.
Code 2: ALU module definition
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` timescale 1 ns / 1 ps
// Module definition
module ALU_ 32 ( A_in , B_in , ALU_ ctrl , ALU_ out , carry_ out , zero , overflow );
// Define I / O ports
// Describe ALU behavior end module // 32 - bit ALU
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Write a testbench for your ALU design and run the tests below. Run each test case for 20 ns.
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Test No.
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A
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in
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B
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in
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ALU
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ctrl
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1
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32’h086a 0c31
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32’hd785 f148
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4’b0000
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2
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32’h086a
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0c31
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32’h1007
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3fd4
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4’b0001
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3
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32’ha86a 0c31
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32’h9007 3fd4
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4’b0010
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4
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32’ha86a
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0c31
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32’h9007
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3fd4
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4’b0110
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5
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32’ha86a 0c31
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32’h9007 3fd4
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4’b0111
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6
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32’ha86a 0c31
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32’h9007 3fd4
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4’b1100
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7
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32’ha86a 0c31
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32’ha86a 0c31
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4’b1111
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8
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32’ha86a 0c31
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32’h1007 3fd4
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4’b1111
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Check the outputs (ALU out, carry out, zero, overflow) to see if they are correct. Put a screenshot of the waveform. in your report. Add more test cases as you wish to make sure your design produces correct outputs for all cases.
3 Assignment Deliverables
Your submission should be in a *.zip file and should be submitted to GradeScope. The ZIP file should include the following items:
• Source Code: ALU module design and testbench. (ALU .v and ALU tb.v)
• PDF Report: A report in the PDF format including the simulation results.
Compress all files (*.v files + report) into one ZIP file named “lab2 UCInetID firstname lastname.zip”
(note: UCInetID is your email user name and it is alphanumeric string), e.g., “lab2 sitaoh sitao huang.zip”, and upload this ZIP file to GradeScope before deadline.
Note 1: Start working on the lab as early as possible.
Note 2: Use the code skeletons given in the lab description. The module part of your code (module name, module declaration, port names, and port declaration) should not be changed.
Note 3: It is fine to discuss the lab with other students, TAs, or AI, but make sure you understand all the details, and you should write your own code.